package naxriscv
import spinal.core._
import naxriscv.compatibility._
import naxriscv.frontend._
import naxriscv.fetch._
import naxriscv.misc._
import naxriscv.execute._
import naxriscv.fetch._
import naxriscv.lsu._
import naxriscv.prediction._
import naxriscv.utilities._
import spinal.lib.{LatencyAnalysis, OHMasking}
import spinal.lib.bus.amba4.axi.Axi4SpecRenamer
import spinal.lib.bus.amba4.axilite.AxiLite4SpecRenamer
import spinal.lib.eda.bench.Rtl
import spinal.lib.misc.WishboneClint
import spinal.lib.misc.plic.WishbonePlic

import scala.collection.mutable.ArrayBuffer
import naxriscv.interfaces.LockedImpl
class Test() extends Component{
  val io = new Bundle{
    val a = in UInt(4 bits)
    val b = in UInt(4 bits)
    val c = out UInt(4 bits)
  }
  class MyPlugin extends Plugin with LockedImpl {
    val early = create early new Area{
      println("run early")
      lock.release()
    }
    val logic = create late new Area{
      lock.retain()
      println("run logic")
      io.c := io.a + io.b
    }
  }
  val framework = new Framework(Seq(new MyPlugin))
}
object mytest extends App{
  val cfg = SpinalConfig(targetDirectory = "generated/test")
  cfg.generateVerilog(new Test)
}

object firstv2 extends App{
  // class First extends Component{
  //   val io = new Bundle{
  //     val a = in Bits(8 bits)
  //     val b = out Bits(8 bits)
  //   }
  //   io.b := OHMasking.firstV2(io.a)
  // }
  // import spinal.core.sim._
  // SimConfig.withWave.doSim(new First){
  //   dut =>
  //     dut.io.a #= Integer.parseInt("1101010", 2)
  //     sleep(200)
  //     dut.io.a #= Integer.parseInt("0011000", 2)
  //     sleep(200)
  //     dut.io.a #= Integer.parseInt("0001000", 2)
  //     sleep(200)
  // }
  // object Test extends Area{
  //   val t = UInt(4 bits)
  // }
  // class Test extends Component{
  //   val io = new Bundle{
  //     val a = in UInt(4 bits)
  //     val c = out Vec(UInt(4 bits), 4)
  //   }
  //   for(i <- 0 until 4){
  //     io.c(i) := io.a.dropLow(i).asUInt
  //   }
  // }
  // SpinalConfig(targetDirectory = "generated/test").generateVerilog(new Test)
  // case class A(a: Int)
  // import scala.collection.mutable.LinkedHashMap
  // val map = LinkedHashMap[A, Int]()
  // map(A(1)) = 1
  // println(map.getOrElse(A(1), 2))
  case class A(num: Int)
  val arr = Array(A(1), A(3), A(-1))
  for(e <- arr.sortWith((x, y) => x.num > y.num)){
    println(e)
  }
}